One form of logic used in integrated circuits is dynamic logic. In general, dynamic logic involves the charging of dynamic nodes to a voltage level representing a high logic state. The dynamic node is then connected to a dynamic logic stage which generally comprises a plurality of transistors forming a plurality of potential paths to ground potential. If the inputs to the dynamic logic stage are such that a current path is created between the dynamic node and ground potential, the voltage level of the dynamic node is reduced and brought to a low logic state. Otherwise, the dynamic node remains at the high logic state. The dynamic node can feed a logic stage, such as an inverter, which can provide an output for the dynamic logic stage. As should be understood, the precharging of the dynamic node provides increased speed for the logic path because the node does not have to be charged to a logic high by the logic devices.
Integrated circuits having dynamic logic can be built upon various forms of conventional structures. For example, dynamic logic can be built in bulk integrated circuits formed in a well within a semiconductor substrate. The dynamic logic can also be built in a silicon-on-insulator environment in which the integrated circuit is formed in a silicon layer deposited above an insulator substrate.
One problem that arises with integrated circuits in general, and dynamic logic in particular, is the fact that a spurious pulse of current can cause an upset of the state of a dynamic node. The spurious pulse can be caused by various factors including voltage fluctuations, alpha particles and cosmic pulses. With silicon-on-insulator (SOI) circuits, a spurious current pulse can be particularly problematic. Typically for SOI transistors, it is desirable to keep the body floating and not tied to a specific voltage potential. In this situation, SOI transistors are susceptible to current leakage from the body to the source due to voltage swings on the source. When leakage occurs, a large drain current can be generated from the drain to the source due to a bipolar-like effect. Such a large drain current can clearly upset charge stored on a drain of such a transistor. Where the transistors that experience such drain current pulses are transistors within a dynamic logic stage, the loss of charge can result in a dynamic node being brought to an incorrect logic level. This can then produce inaccurate logic results for the dynamic logic.
One conventional solution to the problem of spurious pulses is to connect the body of the SOI transistor to ground potential or V.sub.SS. However, a disadvantage of this solution is that it takes up area within the integrated circuit and also reduces the drive current of the transistors. It is preferable to allow the body to float rather than tie it to ground potential.
A second solution is to increase the junction leakage between the body and source of the transistors to avoid a large drain current pulse. This increased junction leakage reduces the beta of the bipolar-like effect thus decreasing the drain current. However, this solution has disadvantages which include the difficulty of providing the correct amount of leakage as well as the standby loss caused by the large junction leakage. Further, such leakage between the body and source reduces the advantage of having the floating body.
Similar problems with current pulses can be generated in bulk integrated circuits by ion strikes, such as alpha particles or cosmic pulses. In bulk transistors, an ion strike in the drain will generate an undesirable current through the drain to well junction. The problem with spurious pulses is not significant for bulk integrated circuits unless the size of the circuits have decreased to the point where capacitances hold charge within the same range as the spurious pulses caused by the ion strike. For example, some DRAM circuits and small scale logic circuits do experience problems created by ion strikes.
With respect to ion strikes, one conventional solution involves the hardening of memory cells such that the logic state of the cell is not altered by ion strikes. One solution for hardening memory cells is to provide delay in the feedback between cross coupled invertors so that the state of the cell does not flip because of a spurious pulse. Examples of such hardened memory cells are disclosed by U.S. Pat. Nos. 4,956,815; 4,912,675; and 4,914,629.